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Welcome to my community at VLSI SYSTEM DESIGN!!
- From: "Kunal Ghosh" <contactvsd at vlsisystemdesign dot com>
- To: cygwin at cygwin dot com
- Date: Fri, 13 Oct 2017 09:46:40 -0400
- Subject: Welcome to my community at VLSI SYSTEM DESIGN!!
- Authentication-results: sourceware.org; auth=none
- Feedback-id: A944546:L3810424:M23844895:AWeber
- X_id: 3810424:1:cygwin at cygwin dot com
Hi
My name is Kunal Ghosh, I am a growth hacker and co-founder at VLSI SYSTEM DESIGN (VSD)
As a 'Growth Hacker', I intend to help students/professionals build their profile even stronger in semiconductors and VLSI, by creating courses at every possible domain in Back end. The experiments which I perform in VSD courses using open-source EDA tools, are of similar complexity of current chip design industry. Till date I have nurtured
around 10000+ students and professionals through videos and many of them have been placed or moved to leading semiconductor industries. I have been doing this part time for past 7 years, and now doing this full time
at VSD. Happy Learning!!
Here's the link to all my ebooks released till now..Download them for FREE
Tri-state buffer characterization:
http://clicks.aweber.com/y/ct/?l=GkX7H&m=3yR80EZOX3A8._6&b=C9cRj8gfkrikrje73qvO7Q
On-chip Variation:
http://clicks.aweber.com/y/ct/?l=GkX7H&m=3yR80EZOX3A8._6&b=f32UC63xFZ8GY8YqTFjX3w
Channel connected component (CCC):
http://clicks.aweber.com/y/ct/?l=GkX7H&m=3yR80EZOX3A8._6&b=r8TiWZTFOrgob_wVKSls8Q
Maze Routing:
http://clicks.aweber.com/y/ct/?l=GkX7H&m=3yR80EZOX3A8._6&b=LwluKnRhTB_ubwwEKDLo2A
Regular buffer v/s clock buffer:
http://clicks.aweber.com/y/ct/?l=GkX7H&m=3yR80EZOX3A8._6&b=S2z1bApHsh.kVKBg5O6eqQ
Few more static power:
http://clicks.aweber.com/y/ct/?l=GkX7H&m=3yR80EZOX3A8._6&b=WbrjInZeIMnOmAOMyFVxig
Propagated noise:
http://clicks.aweber.com/y/ct/?l=GkX7H&m=3yR80EZOX3A8._6&b=t10Z38gO6aZOH3Sb1xQHuA
CPPR:
http://clicks.aweber.com/y/ct/?l=GkX7H&m=3yR80EZOX3A8._6&b=n_qcjCEPgIca4Kwrh4_qsg
Industrial Physical design flow (my IITB college notes which helped me get into my first job)
http://clicks.aweber.com/y/ct/?l=GkX7H&m=3yR80EZOX3A8._6&b=50O18eoI9jtQa2Qj.Z83OA
Clock gating analysis:
http://clicks.aweber.com/y/ct/?l=GkX7H&m=3yR80EZOX3A8._6&b=UqIMlPaJKIJBIgt7AXvD3g
SPEF parasitic format explained in detail:
http://clicks.aweber.com/y/ct/?l=GkX7H&m=3yR80EZOX3A8._6&b=ijhHdA_qSdQX_h.EZAWENg
Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:
1) VSD - Physical design flow
2) VSD - Clock tree synthesis - Part 1 & 2
3) VSD - Signal Integrity
4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)
5) VSD - Circuit design and SPICE simulations Part 1 & Part 2
(This is the core of VLSI, so you can take it in beginning or end)
6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)
7) VSD - Custom Layout (Can be taken in between)
Connect with me for more guidance:
Hope you enjoy the session best of luck for future !!
Outer Ring Road
Bangalore
Bangalore Karnataka 560037
INDIA
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